Major DRAM Suppliers Join in Development of SyncLink Architecture; Consortium Proposes DRAM Standard, Reveals Timeline

The SyncLink Consortium today announced that it has delivered the draft of a new dynamic random-access memory (DRAM) architecture specification to the IEEE P1596.7 SyncLink Working Group, which is developing an open, royalty-free industry standard for high-performance DRAMs.

At the same time, the Consortium revealed the timeline for production of devices conforming to the new standard.

The new SyncLink DRAM, or SLDRAM, architecture will allow memory manufacturers to create low-cost, extremely high-performance memories. For example, the proposed standard, which will be known as IEEE Standard 1596.7 SyncLink, specifies an architecture that supports a 64M-bit memory with a data transfer rate of 1.6 gigabytes per second.

A primary potential application for such devices is in the main memory of personal computers and workstations, which is estimated to account for up to 80 percent of all DRAM usage. The SLDRAM will enable the next generations of such systems.

The SyncLink Architecture

SyncLink is an evolutionary step beyond today's Synchronous DRAM (SDRAM). SyncLink architecture packetizes and pipelines the address, commands, and their timing, and adds features that significantly increase the data bus speed, providing fast memory access without losing the ability to move quickly from row to row or to obtain bursts of data.

A 10-bit upper bus is used for command and address transmission to the SLDRAM chip, and an 18-bit lower bus is used for data signals. The use of separate buses, and the low latency produced by the architecture, will result in memories having unsurpassed performance levels, an advantage that can be passed on to the end user.

The SyncLink Timeline

The timeline announced by the Consortium calls for the first SLDRAMs to be available in the second half of 1997.

The SyncLink Consortium

The SyncLink Consortium members include nine of the top DRAM suppliers, bringing together companies with commodities manufacturing expertise and a combined DRAM marketshare of 75% worldwide. They are Fujitsu Microelectronics, Hyundai Electronics, IBM Microelectronics, Micron Technology, Mitsubishi Electronics America, NEC, Nippon Steel Corp., Samsung Electronics, and Texas Instruments.

The combined capabilities of these companies will ensure that the benefits of mass production volumes are achieved in a timely manner. Other members include Apple Computer, Hewlett Packard, IBM Corp., and MOSAID Technologies Inc. Consortium membership is available to all interested companies, with membership fees presently in the range of $25,000 to $50,000 per year.

Beyond working together to develop the new SyncLink standard, the Consortium members intend to support the standard with tools that will make it easier to use, and to cooperate in marketing and promoting the standard.

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